s known as register, data register, vector register, general purpose register, general purpose vector register (VGPR)
* 32bit data is most common input/output argument
* R255 is the special "Zero" registers "RZ". RZ reads 0x0, RZ ignores writes (for disabling output arguments)
* named "vector" register because every thread in warp has its own data

references:
* https://p4viewer.nvidia.com/get/hw/doc/gpu/maxwell/maxwell/design/IAS/SM/ISA/IAS_Maxwell_ISA.htm#Instruction_Source_And_Destination_Operands
* https://p4viewer.nvidia.com/get/hw/doc/gpu/volta/volta/design/IAS/SM/ISA/IAS_Volta_ISA.htm#Architecture_State__Registers
* https://p4viewer.nvidia.com/get/hw/doc/gpu/turing/turing/design/IAS/SM/ISA/IAS_Turing_ISA.htm#Architecture_State__Registers
* https://p4viewer.nvidia.com/get/hw/doc/gpu/ampere/ampere/design/IAS/SM/ISA/IAS_Ampere_ISA.htm#Architecture_State__Registers