tes PR/P0-P7, Condition Codes CC.OF/CF/SF/ZF, and UPR/UP0-UP7 using P2R/UP2UR

Volta/SM7.0 and later removed condition codes in favor of regular predicates.

references:
* https://p4viewer.nvidia.com/get/hw/doc/gpu/maxwell/maxwell/design/IAS/SM/ISA/opcodes/opP2R.htm
* https://p4viewer.nvidia.com/get/hw/doc/gpu/volta/volta/design/IAS/SM/ISA/opcodes/opP2R.htm
* https://p4viewer.nvidia.com/get/hw/doc/gpu/turing/turing/design/IAS/SM/ISA/opcodes/opP2R.htm
* https://p4viewer.nvidia.com/get/hw/doc/gpu/ampere/ampere/design/IAS/SM/ISA/opcodes/opP2R.htm
* https://p4viewer.nvidia.com/get/hw/doc/gpu/maxwell/maxwell/design/IAS/SM/ISA/IAS_Maxwell_ISA.htm#SM_Predicates
* https://p4viewer.nvidia.com/get/hw/doc/gpu/maxwell/maxwell/design/IAS/SM/ISA/IAS_Maxwell_ISA.htm#SM_Condition_Codes
* https://p4viewer.nvidia.com/get/hw/doc/gpu/volta/volta/design/IAS/SM/ISA/IAS_Volta_ISA.htm#Architecture_State__Predicates
* https://p4viewer.nvidia.com/get/hw/doc/gpu/turing/turing/design/IAS/SM/ISA/IAS_Turing_ISA.htm#Architecture_State__Predicates
* https://p4viewer.nvidia.com/get/hw/doc/gpu/ampere/ampere/design/IAS/SM/ISA/IAS_Ampere_ISA.htm#Architecture_State__Predicates