iewer.nvidia.com/get/hw/doc/gpu/ampere/ampere/design/IAS/SM/ISA/opcodes/opB2R.htm
* https://p4viewer.nvidia.com/get/hw/doc/gpu/maxwell/maxwell/design/IAS/SM/ISA/IAS_Maxwell_ISA.htm#SM_Barriers
* https://p4viewer.nvidia.com/get/hw/doc/gpu/volta/volta/design/IAS/SM/ISA/IAS_Volta_ISA.htm#Architecture_State__Barriers
* https://p4viewer.nvidia.com/get/hw/doc/gpu/turing/turing/design/IAS/SM/ISA/IAS_Turing_ISA.htm#Architecture_State__Barriers
* https://p4viewer.nvidia.com/get/hw/doc/gpu/ampere/ampere/design/IAS/SM/ISA/IAS_Ampere_ISA.htm#Architecture_State__CTA_Barriers