.version 7.8
.target sm_80
.address_size 64

	// .globl	activation_4
.visible .const .align 4 .b8 params[8];

.visible .func  (.param .align 4 .b8 func_retval0[16]) activation_4(
	.param .align 4 .b8 activation_4_param_0[16]
)
{
.pragma "abi_param_reg all";
	.reg .pred 	%p<17>;
	.reg .b16 	%rs<35>;
	.reg .f32 	%f<217>;
	.reg .b32 	%r<41>;


	ld.param.f32 	%f1, [activation_4_param_0];
	mov.b32 	%r1, %f1;
	ld.param.f32 	%f4, [activation_4_param_0+12];
	ld.param.f32 	%f3, [activation_4_param_0+8];
	ld.param.f32 	%f2, [activation_4_param_0+4];
	mov.b32 	{%rs19, %rs2}, %r1;
	// begin inline asm
	{  cvt.f32.f16 %f45, %rs19;}

	// end inline asm
	abs.ftz.f32 	%f6, %f45;
	setp.ltu.ftz.f32 	%p1, %f6, 0f3F19999A;
	@%p1 bra 	$L__BB0_2;
	bra.uni 	$L__BB0_1;

$L__BB0_2:
	mul.ftz.f32 	%f54, %f45, %f45;
	mov.f32 	%f55, 0fBD563CAE;
	mov.f32 	%f56, 0f3C80F082;
	fma.rn.ftz.f32 	%f57, %f56, %f54, %f55;
	mov.f32 	%f58, 0f3E085941;
	fma.rn.ftz.f32 	%f59, %f57, %f54, %f58;
	mov.f32 	%f60, 0fBEAAA9ED;
	fma.rn.ftz.f32 	%f61, %f59, %f54, %f60;
	mov.f32 	%f62, 0f00000000;
	fma.rn.ftz.f32 	%f63, %f61, %f54, %f62;
	fma.rn.ftz.f32 	%f209, %f63, %f45, %f45;
	bra.uni 	$L__BB0_3;

$L__BB0_1:
	mul.ftz.f32 	%f46, %f6, 0f4038AA3B;
	ex2.approx.ftz.f32 	%f47, %f46;
	add.ftz.f32 	%f48, %f47, 0f3F800000;
	mov.f32 	%f49, 0f3F800000;
	rcp.approx.ftz.f32 	%f50, %f48;
	mov.f32 	%f51, 0fC0000000;
	fma.rn.ftz.f32 	%f52, %f50, %f51, %f49;
	setp.ge.ftz.f32 	%p2, %f6, 0f41102CB4;
	selp.f32 	%f53, 0f3F800000, %f52, %p2;
	mov.b32 	%r2, %f53;
	mov.b32 	%r3, %f45;
	and.b32  	%r4, %r3, -2147483648;
	or.b32  	%r5, %r4, %r2;
	mov.b32 	%f209, %r5;

$L__BB0_3:
	// begin inline asm
	{  cvt.rn.f16.f32 %rs20, %f209;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f65, %rs2;}

	// end inline asm
	abs.ftz.f32 	%f11, %f65;
	setp.ltu.ftz.f32 	%p3, %f11, 0f3F19999A;
	@%p3 bra 	$L__BB0_5;
	bra.uni 	$L__BB0_4;

$L__BB0_5:
	mul.ftz.f32 	%f74, %f65, %f65;
	mov.f32 	%f75, 0fBD563CAE;
	mov.f32 	%f76, 0f3C80F082;
	fma.rn.ftz.f32 	%f77, %f76, %f74, %f75;
	mov.f32 	%f78, 0f3E085941;
	fma.rn.ftz.f32 	%f79, %f77, %f74, %f78;
	mov.f32 	%f80, 0fBEAAA9ED;
	fma.rn.ftz.f32 	%f81, %f79, %f74, %f80;
	mov.f32 	%f82, 0f00000000;
	fma.rn.ftz.f32 	%f83, %f81, %f74, %f82;
	fma.rn.ftz.f32 	%f210, %f83, %f65, %f65;
	bra.uni 	$L__BB0_6;

$L__BB0_4:
	mul.ftz.f32 	%f66, %f11, 0f4038AA3B;
	ex2.approx.ftz.f32 	%f67, %f66;
	add.ftz.f32 	%f68, %f67, 0f3F800000;
	mov.f32 	%f69, 0f3F800000;
	rcp.approx.ftz.f32 	%f70, %f68;
	mov.f32 	%f71, 0fC0000000;
	fma.rn.ftz.f32 	%f72, %f70, %f71, %f69;
	setp.ge.ftz.f32 	%p4, %f11, 0f41102CB4;
	selp.f32 	%f73, 0f3F800000, %f72, %p4;
	mov.b32 	%r6, %f73;
	mov.b32 	%r7, %f65;
	and.b32  	%r8, %r7, -2147483648;
	or.b32  	%r9, %r8, %r6;
	mov.b32 	%f210, %r9;

$L__BB0_6:
	// begin inline asm
	{  cvt.rn.f16.f32 %rs22, %f210;}

	// end inline asm
	mov.b32 	%r10, %f2;
	mov.b32 	{%rs23, %rs7}, %r10;
	// begin inline asm
	{  cvt.f32.f16 %f85, %rs23;}

	// end inline asm
	abs.ftz.f32 	%f16, %f85;
	setp.ltu.ftz.f32 	%p5, %f16, 0f3F19999A;
	@%p5 bra 	$L__BB0_8;
	bra.uni 	$L__BB0_7;

$L__BB0_8:
	mul.ftz.f32 	%f94, %f85, %f85;
	mov.f32 	%f95, 0fBD563CAE;
	mov.f32 	%f96, 0f3C80F082;
	fma.rn.ftz.f32 	%f97, %f96, %f94, %f95;
	mov.f32 	%f98, 0f3E085941;
	fma.rn.ftz.f32 	%f99, %f97, %f94, %f98;
	mov.f32 	%f100, 0fBEAAA9ED;
	fma.rn.ftz.f32 	%f101, %f99, %f94, %f100;
	mov.f32 	%f102, 0f00000000;
	fma.rn.ftz.f32 	%f103, %f101, %f94, %f102;
	fma.rn.ftz.f32 	%f211, %f103, %f85, %f85;
	bra.uni 	$L__BB0_9;

$L__BB0_7:
	mul.ftz.f32 	%f86, %f16, 0f4038AA3B;
	ex2.approx.ftz.f32 	%f87, %f86;
	add.ftz.f32 	%f88, %f87, 0f3F800000;
	mov.f32 	%f89, 0f3F800000;
	rcp.approx.ftz.f32 	%f90, %f88;
	mov.f32 	%f91, 0fC0000000;
	fma.rn.ftz.f32 	%f92, %f90, %f91, %f89;
	setp.ge.ftz.f32 	%p6, %f16, 0f41102CB4;
	selp.f32 	%f93, 0f3F800000, %f92, %p6;
	mov.b32 	%r11, %f93;
	mov.b32 	%r12, %f85;
	and.b32  	%r13, %r12, -2147483648;
	or.b32  	%r14, %r13, %r11;
	mov.b32 	%f211, %r14;

$L__BB0_9:
	// begin inline asm
	{  cvt.rn.f16.f32 %rs24, %f211;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f105, %rs7;}

	// end inline asm
	abs.ftz.f32 	%f21, %f105;
	setp.ltu.ftz.f32 	%p7, %f21, 0f3F19999A;
	@%p7 bra 	$L__BB0_11;
	bra.uni 	$L__BB0_10;

$L__BB0_11:
	mul.ftz.f32 	%f114, %f105, %f105;
	mov.f32 	%f115, 0fBD563CAE;
	mov.f32 	%f116, 0f3C80F082;
	fma.rn.ftz.f32 	%f117, %f116, %f114, %f115;
	mov.f32 	%f118, 0f3E085941;
	fma.rn.ftz.f32 	%f119, %f117, %f114, %f118;
	mov.f32 	%f120, 0fBEAAA9ED;
	fma.rn.ftz.f32 	%f121, %f119, %f114, %f120;
	mov.f32 	%f122, 0f00000000;
	fma.rn.ftz.f32 	%f123, %f121, %f114, %f122;
	fma.rn.ftz.f32 	%f212, %f123, %f105, %f105;
	bra.uni 	$L__BB0_12;

$L__BB0_10:
	mul.ftz.f32 	%f106, %f21, 0f4038AA3B;
	ex2.approx.ftz.f32 	%f107, %f106;
	add.ftz.f32 	%f108, %f107, 0f3F800000;
	mov.f32 	%f109, 0f3F800000;
	rcp.approx.ftz.f32 	%f110, %f108;
	mov.f32 	%f111, 0fC0000000;
	fma.rn.ftz.f32 	%f112, %f110, %f111, %f109;
	setp.ge.ftz.f32 	%p8, %f21, 0f41102CB4;
	selp.f32 	%f113, 0f3F800000, %f112, %p8;
	mov.b32 	%r15, %f113;
	mov.b32 	%r16, %f105;
	and.b32  	%r17, %r16, -2147483648;
	or.b32  	%r18, %r17, %r15;
	mov.b32 	%f212, %r18;

$L__BB0_12:
	// begin inline asm
	{  cvt.rn.f16.f32 %rs26, %f212;}

	// end inline asm
	mov.b32 	%r19, %f3;
	mov.b32 	{%rs27, %rs12}, %r19;
	// begin inline asm
	{  cvt.f32.f16 %f125, %rs27;}

	// end inline asm
	abs.ftz.f32 	%f26, %f125;
	setp.ltu.ftz.f32 	%p9, %f26, 0f3F19999A;
	@%p9 bra 	$L__BB0_14;
	bra.uni 	$L__BB0_13;

$L__BB0_14:
	mul.ftz.f32 	%f134, %f125, %f125;
	mov.f32 	%f135, 0fBD563CAE;
	mov.f32 	%f136, 0f3C80F082;
	fma.rn.ftz.f32 	%f137, %f136, %f134, %f135;
	mov.f32 	%f138, 0f3E085941;
	fma.rn.ftz.f32 	%f139, %f137, %f134, %f138;
	mov.f32 	%f140, 0fBEAAA9ED;
	fma.rn.ftz.f32 	%f141, %f139, %f134, %f140;
	mov.f32 	%f142, 0f00000000;
	fma.rn.ftz.f32 	%f143, %f141, %f134, %f142;
	fma.rn.ftz.f32 	%f213, %f143, %f125, %f125;
	bra.uni 	$L__BB0_15;

$L__BB0_13:
	mul.ftz.f32 	%f126, %f26, 0f4038AA3B;
	ex2.approx.ftz.f32 	%f127, %f126;
	add.ftz.f32 	%f128, %f127, 0f3F800000;
	mov.f32 	%f129, 0f3F800000;
	rcp.approx.ftz.f32 	%f130, %f128;
	mov.f32 	%f131, 0fC0000000;
	fma.rn.ftz.f32 	%f132, %f130, %f131, %f129;
	setp.ge.ftz.f32 	%p10, %f26, 0f41102CB4;
	selp.f32 	%f133, 0f3F800000, %f132, %p10;
	mov.b32 	%r20, %f133;
	mov.b32 	%r21, %f125;
	and.b32  	%r22, %r21, -2147483648;
	or.b32  	%r23, %r22, %r20;
	mov.b32 	%f213, %r23;

$L__BB0_15:
	// begin inline asm
	{  cvt.rn.f16.f32 %rs28, %f213;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f145, %rs12;}

	// end inline asm
	abs.ftz.f32 	%f31, %f145;
	setp.ltu.ftz.f32 	%p11, %f31, 0f3F19999A;
	@%p11 bra 	$L__BB0_17;
	bra.uni 	$L__BB0_16;

$L__BB0_17:
	mul.ftz.f32 	%f154, %f145, %f145;
	mov.f32 	%f155, 0fBD563CAE;
	mov.f32 	%f156, 0f3C80F082;
	fma.rn.ftz.f32 	%f157, %f156, %f154, %f155;
	mov.f32 	%f158, 0f3E085941;
	fma.rn.ftz.f32 	%f159, %f157, %f154, %f158;
	mov.f32 	%f160, 0fBEAAA9ED;
	fma.rn.ftz.f32 	%f161, %f159, %f154, %f160;
	mov.f32 	%f162, 0f00000000;
	fma.rn.ftz.f32 	%f163, %f161, %f154, %f162;
	fma.rn.ftz.f32 	%f214, %f163, %f145, %f145;
	bra.uni 	$L__BB0_18;

$L__BB0_16:
	mul.ftz.f32 	%f146, %f31, 0f4038AA3B;
	ex2.approx.ftz.f32 	%f147, %f146;
	add.ftz.f32 	%f148, %f147, 0f3F800000;
	mov.f32 	%f149, 0f3F800000;
	rcp.approx.ftz.f32 	%f150, %f148;
	mov.f32 	%f151, 0fC0000000;
	fma.rn.ftz.f32 	%f152, %f150, %f151, %f149;
	setp.ge.ftz.f32 	%p12, %f31, 0f41102CB4;
	selp.f32 	%f153, 0f3F800000, %f152, %p12;
	mov.b32 	%r24, %f153;
	mov.b32 	%r25, %f145;
	and.b32  	%r26, %r25, -2147483648;
	or.b32  	%r27, %r26, %r24;
	mov.b32 	%f214, %r27;

$L__BB0_18:
	// begin inline asm
	{  cvt.rn.f16.f32 %rs30, %f214;}

	// end inline asm
	mov.b32 	%r28, %f4;
	mov.b32 	{%rs31, %rs17}, %r28;
	// begin inline asm
	{  cvt.f32.f16 %f165, %rs31;}

	// end inline asm
	abs.ftz.f32 	%f36, %f165;
	setp.ltu.ftz.f32 	%p13, %f36, 0f3F19999A;
	@%p13 bra 	$L__BB0_20;
	bra.uni 	$L__BB0_19;

$L__BB0_20:
	mul.ftz.f32 	%f174, %f165, %f165;
	mov.f32 	%f175, 0fBD563CAE;
	mov.f32 	%f176, 0f3C80F082;
	fma.rn.ftz.f32 	%f177, %f176, %f174, %f175;
	mov.f32 	%f178, 0f3E085941;
	fma.rn.ftz.f32 	%f179, %f177, %f174, %f178;
	mov.f32 	%f180, 0fBEAAA9ED;
	fma.rn.ftz.f32 	%f181, %f179, %f174, %f180;
	mov.f32 	%f182, 0f00000000;
	fma.rn.ftz.f32 	%f183, %f181, %f174, %f182;
	fma.rn.ftz.f32 	%f215, %f183, %f165, %f165;
	bra.uni 	$L__BB0_21;

$L__BB0_19:
	mul.ftz.f32 	%f166, %f36, 0f4038AA3B;
	ex2.approx.ftz.f32 	%f167, %f166;
	add.ftz.f32 	%f168, %f167, 0f3F800000;
	mov.f32 	%f169, 0f3F800000;
	rcp.approx.ftz.f32 	%f170, %f168;
	mov.f32 	%f171, 0fC0000000;
	fma.rn.ftz.f32 	%f172, %f170, %f171, %f169;
	setp.ge.ftz.f32 	%p14, %f36, 0f41102CB4;
	selp.f32 	%f173, 0f3F800000, %f172, %p14;
	mov.b32 	%r29, %f173;
	mov.b32 	%r30, %f165;
	and.b32  	%r31, %r30, -2147483648;
	or.b32  	%r32, %r31, %r29;
	mov.b32 	%f215, %r32;

$L__BB0_21:
	// begin inline asm
	{  cvt.rn.f16.f32 %rs32, %f215;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f185, %rs17;}

	// end inline asm
	abs.ftz.f32 	%f41, %f185;
	setp.ltu.ftz.f32 	%p15, %f41, 0f3F19999A;
	@%p15 bra 	$L__BB0_23;
	bra.uni 	$L__BB0_22;

$L__BB0_23:
	mul.ftz.f32 	%f194, %f185, %f185;
	mov.f32 	%f195, 0fBD563CAE;
	mov.f32 	%f196, 0f3C80F082;
	fma.rn.ftz.f32 	%f197, %f196, %f194, %f195;
	mov.f32 	%f198, 0f3E085941;
	fma.rn.ftz.f32 	%f199, %f197, %f194, %f198;
	mov.f32 	%f200, 0fBEAAA9ED;
	fma.rn.ftz.f32 	%f201, %f199, %f194, %f200;
	mov.f32 	%f202, 0f00000000;
	fma.rn.ftz.f32 	%f203, %f201, %f194, %f202;
	fma.rn.ftz.f32 	%f216, %f203, %f185, %f185;
	bra.uni 	$L__BB0_24;

$L__BB0_22:
	mul.ftz.f32 	%f186, %f41, 0f4038AA3B;
	ex2.approx.ftz.f32 	%f187, %f186;
	add.ftz.f32 	%f188, %f187, 0f3F800000;
	mov.f32 	%f189, 0f3F800000;
	rcp.approx.ftz.f32 	%f190, %f188;
	mov.f32 	%f191, 0fC0000000;
	fma.rn.ftz.f32 	%f192, %f190, %f191, %f189;
	setp.ge.ftz.f32 	%p16, %f41, 0f41102CB4;
	selp.f32 	%f193, 0f3F800000, %f192, %p16;
	mov.b32 	%r33, %f193;
	mov.b32 	%r34, %f185;
	and.b32  	%r35, %r34, -2147483648;
	or.b32  	%r36, %r35, %r33;
	mov.b32 	%f216, %r36;

$L__BB0_24:
	// begin inline asm
	{  cvt.rn.f16.f32 %rs34, %f216;}

	// end inline asm
	mov.b32 	%r37, {%rs32, %rs34};
	mov.b32 	%r38, {%rs20, %rs22};
	mov.b32 	%r39, {%rs24, %rs26};
	mov.b32 	%r40, {%rs28, %rs30};
	mov.b32 	%f205, %r37;
	mov.b32 	%f206, %r40;
	mov.b32 	%f207, %r39;
	mov.b32 	%f208, %r38;
	st.param.f32 	[func_retval0+0], %f208;
	st.param.f32 	[func_retval0+4], %f207;
	st.param.f32 	[func_retval0+8], %f206;
	st.param.f32 	[func_retval0+12], %f205;
	ret;

}