%r<16>;
	.reg .b64 	%rd<52>;


	mov.b64 	%rd20, ConvertTensor_nosmem_param_0;
	mov.u64 	%rd2, %rd20;
	mov.u32 	%r1, %ctaid.x;
	shl.b32 	%r2, %r1, 8;
	mov.u32 	%r3, %tid.x;
	add.s32 	%r4, %r2, %r3;
	cvt.u64.u32 	%rd1, %r4;
	ld.param.u64 	%rd3, [ConvertTensor_nosmem_param_0+88];
	and.b64  	%rd21, %rd3, -4294967296;
	setp.eq.s64 	%p1, %rd21, 0;
	@%p1 bra 	$L__BB0_2;

	div.u64 	%rd50, %rd1, %rd3;
	mul.lo.s64 	%rd22, %rd50, %rd3;
	sub.s64 	%rd51, %rd1, %rd22;
	bra.uni 	$L__BB0_3;

$L__BB0_2:
	cvt.u32.u64 	%r5, %rd3;
	cvt.u32.u64 	%r6, %rd1;
	div.u32 	%r7, %r6, %r5;
	mul.lo.s32 	%r8, %r7, %r5;
	sub.s32 	%r9, %r6, %r8;
	cvt.u64.u32 	%rd50, %r7;
	cvt.u64.u32 	%rd51, %r9;

$L__BB0_3:
	cvt.u32.u64 	%r11, %rd50;
	shl.b32 	%r12, %r11, 1;
	ld.param.u64 	%rd23, [%rd2+8];
	cvta.to.global.u64 	%rd10, %rd23;
	ld.param.u64 	%rd24, [%rd2+48];
	mov.u32 	%r13, %ctaid.y;
	cvt.u64.u32 	%rd25, %r13;
	mul.lo.s64 	%rd11, %rd24, %rd25;
	ld.param.u64 	%rd12, [%rd2+72];
	ld.param.u64 	%rd26, [%rd2+56];
	mul.lo.s64 	%rd13, %rd26, %rd51;
	ld.param.u64 	%rd27, [%rd2];
	cvta.to.global.u64 	%rd14, %rd27;
	ld.param.u64 	%rd28, [%rd2+112];
	mul.lo.s64 	%rd29, %rd28, %rd25;
	ld.param.u64 	%rd30, [%rd2+120];
	mul.lo.s64 	%rd31, %rd30, %rd51;
	add.s64 	%rd15, %rd31, %rd29;
	ld.param.u64 	%rd16, [%rd2+136];
	cvt.u64.u32 	%rd17, %r12;
	ld.param.u64 	%rd18, [%rd2+160];
	setp.le.u64 	%p2, %rd18, %rd17;
	@%p2 bra 	$L__BB0_5;

	mul.lo.s64 	%rd32, %rd12, %rd17;
	add.s64 	%rd33, %rd32, %rd11;
	add.s64 	%rd34, %rd33, %rd13;
	shl.b64 	%rd35, %rd34, 1;
	add.s64 	%rd36, %rd10, %rd35;
	ld.global.u16 	%rs2, [%rd36];
	mul.lo.s64 	%rd37, %rd16, %rd17;
	add.s64 	%rd38, %rd15, %rd37;
	shl.b64 	%rd39, %rd38, 1;
	add.s64 	%rd40, %rd14, %rd39;
	st.global.u16 	[%rd40], %rs2;

$L__BB0_5:
	cvt.u32.u64 	%r14, %rd17;
	add.s32 	%r15, %r14, 1;
	cvt.u64.u32 	%rd19, %r15;
	setp.le.u64 	%p3, %rd18, %rd19;
	@%p3 bra 	$L__BB0_7;

	mul.lo.s64 	%rd41, %rd12, %rd19;
	add.s64 	%rd42, %rd41, %rd11;
	add.s64 	%rd43, %rd42, %rd13;
	shl.b64 	%rd44, %rd43, 1;
	add.s64 	%rd45, %rd10, %rd44;
	ld.global.u16 	%rs3, [%rd45];
	mul.lo.s64 	%rd46, %rd16, %rd19;
	add.s64 	%rd47, %rd15, %rd46;
	shl.b64 	%rd48, %rd47, 1;
	add.s64 	%rd49, %rd14, %rd48;
	st.global.u16 	[%rd49], %rs3;

$L__BB0_7:
	ret;

}